instruction buffer
英 [ɪnˈstrʌkʃn ˈbʌfə(r)]
美 [ɪnˈstrʌkʃn ˈbʌfər]
网络 指令缓存器; 指令缓冲器; 指令缓冲区
双语例句
- Note that you used the ila instruction(" immediate load address") to load the address of the buffer.
注意，这里使用了ila指令（意思是“immediateloadaddress”）来加载缓冲区的地址。 - An overlay arrow points to the current instruction, and you can set and remove breakpoints as with the source buffer.
有一个箭头指向当前指令，你可以像在源代码buffer中一样设置和清除断点。 - An instruction buffer based on the stated FIFO is applied in an embedded Java processor, and such design proved to be effective for enhancing the efficiency of the instruction fetch operation while the Java byte code verifies in real time, and for facilitating the instruction folding operation.
该设计在一种针对嵌入式系统的Java虚拟机的硬件实现中得到应用，提高了Java处理的取指效率，并对随后的指令折叠提供了方便。 - A Low-Power Instruction Cache Design Based on Record Buffer
基于记录缓冲的低功耗指令Cache方案 - The encoding unit, composed of instruction buffer and command encoder, translates the 12-bit command code to 16-bit control signal, and ensures each part of the system to work steadily.
译码单元由指令缓存器和指令译码器构成，针对12位的指令代码翻译成16位控制信号，传送给处理器内部各个部件，用以保证各部件正常工作。 - Performance Analysis of Instruction Buffer Management in the Interpreter in Binary Translation
二进制翻译中解释器指令缓冲区管理策略分析 - Test and performance analysis show that the dynamic instruction pipeline of the Godson 1 processor is efficient and its security design can effectively defense network attack based on buffer overflow technique.
测试表明龙芯1号处理器的指令流水线效率高，其安全设计能有效防范使用缓冲区溢出技术进行的网络攻击。 - In FPGA, CPU IP Core have necessary arithmetic logic unit ( ALU), register stack, instruction buffer, Jump-counter, instruction-set, and optimize the performance of CPU based on the architecture of FPGA.
在FPGA内部不仅实现了CPU必需的算术逻辑器、寄存器堆、指令缓冲、跳转计数、指令集，而且针对FPGA内部的结构特点对设计进行了地址和数据的优化。 - Based on these information, make the attack code accepts the buffer boundary check, stack boundary check, return address check and jump instruction check, intercept attacks on the key nodes of buffer overflow attacks, enhance system dynamic security.
依据这些信息，对攻击行为执行缓冲区边界检查，栈边界检查，返回地址保护和跳转指令检查，在缓冲区溢出攻击流程的关键节点拦截攻击，增强系统运行过程中的安全性。 - The instruction Cache design included the design of basic parameter, instruction Cache architecture, each functional module and Line Buffer.
对于指令Cache的设计主要包括基本参数的设计，指令Cache体系结构的设计，各个功能模块的设计，以及LineBuffer的设计。